Emacs : verilog-mode snippets fix.✡

.doom.d/snippets/verilog-mode/always(async rst)

@@ -1,10 +1,7 @@
 # -*- mode: snippet -*-
-# name: always (asynchronous rst)
+# name: always(async rst)
-# uuid:
+# key:
-# key: trigger-key
-# condition: t
 # --
-
 always@(posedge clk or posedge rst)
 if(rst) begin
 /*AUTORESET*/

.doom.d/snippets/verilog-mode/always(async rstn)

@@ -1,10 +1,7 @@
 # -*- mode: snippet -*-
-# name: always (asynchronous rstn)
+# name: always(async rstn)
-# uuid:
+# key:
-# key: trigger-key
-# condition: t
 # --
-
 always@(posedge clk or negedge rstn)
 if(!rstn) begin
 /*AUTORESET*/

.doom.d/snippets/verilog-mode/always(sync rst)

@@ -1,10 +1,7 @@
 # -*- mode: snippet -*-
-# name: always (synchronous rst)
+# name: always(sync rst)
-# uuid:
+# key:
-# key: trigger-key
-# condition: t
 # --
-
 always@(posedge clk)
 if(rst) begin
 /*AUTORESET*/

.doom.d/snippets/verilog-mode/always(sync rstn)

@@ -1,10 +1,7 @@
 # -*- mode: snippet -*-
-# name: always (synchronous rstn)
+# name: always(sync rstn)
-# uuid:
+# key:
-# key: trigger-key
-# condition: t
 # --
-
 always@(posedge clk)
 if(!rstn) begin
 /*AUTORESET*/

.doom.d/snippets/verilog-mode/module(base)

@@ -1,10 +1,7 @@
 # -*- mode: snippet -*-
 # name: module(base)
-# uuid:
+# key:
-# key: trigger-key
-# condition: t
 # --
-
 module example
 #(
 parameter DIN_LEN = 8