From d727c170f58e118e85b29e7bc3f2251c57d6d313 Mon Sep 17 00:00:00 2001
From: JaeYoo-Im <cpu3792@gmail.com>
Date: Mon, 13 Jun 2022 12:01:46 +0900
Subject: [PATCH] =?UTF-8?q?Emacs=20:=20verilog-mode=20snippets=20fix.?=
 =?UTF-8?q?=E2=9C=A1?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 .../{always (asynchronous rst) => always(async rst)}     | 9 +++------
 .../{always (asynchronous rstn) => always(async rstn)}   | 9 +++------
 .../{always (synchronous rst) => always(sync rst)}       | 9 +++------
 .../{always (synchronous rstn) => always(sync rstn)}     | 9 +++------
 .doom.d/snippets/verilog-mode/module(base)               | 7 ++-----
 5 files changed, 14 insertions(+), 29 deletions(-)
 rename .doom.d/snippets/verilog-mode/{always (asynchronous rst) => always(async rst)} (58%)
 mode change 100644 => 100755
 rename .doom.d/snippets/verilog-mode/{always (asynchronous rstn) => always(async rstn)} (58%)
 mode change 100644 => 100755
 rename .doom.d/snippets/verilog-mode/{always (synchronous rst) => always(sync rst)} (55%)
 mode change 100644 => 100755
 rename .doom.d/snippets/verilog-mode/{always (synchronous rstn) => always(sync rstn)} (55%)
 mode change 100644 => 100755
 mode change 100644 => 100755 .doom.d/snippets/verilog-mode/module(base)

diff --git a/.doom.d/snippets/verilog-mode/always (asynchronous rst) b/.doom.d/snippets/verilog-mode/always(async rst)
old mode 100644
new mode 100755
similarity index 58%
rename from .doom.d/snippets/verilog-mode/always (asynchronous rst)
rename to .doom.d/snippets/verilog-mode/always(async rst)
index dcc5120..2a59ebd
--- a/.doom.d/snippets/verilog-mode/always (asynchronous rst)	
+++ b/.doom.d/snippets/verilog-mode/always(async rst)	
@@ -1,14 +1,11 @@
 # -*- mode: snippet -*-
-# name: always (asynchronous rst)
-# uuid:
-# key: trigger-key
-# condition: t
+# name: always(async rst)
+# key:
 # --
-
 always@(posedge clk or posedge rst)
 if(rst) begin
 /*AUTORESET*/
 end
 else begin
 end
-end
\ No newline at end of file
+end
diff --git a/.doom.d/snippets/verilog-mode/always (asynchronous rstn) b/.doom.d/snippets/verilog-mode/always(async rstn)
old mode 100644
new mode 100755
similarity index 58%
rename from .doom.d/snippets/verilog-mode/always (asynchronous rstn)
rename to .doom.d/snippets/verilog-mode/always(async rstn)
index dd41bd1..4743883
--- a/.doom.d/snippets/verilog-mode/always (asynchronous rstn)	
+++ b/.doom.d/snippets/verilog-mode/always(async rstn)	
@@ -1,14 +1,11 @@
 # -*- mode: snippet -*-
-# name: always (asynchronous rstn)
-# uuid:
-# key: trigger-key
-# condition: t
+# name: always(async rstn)
+# key:
 # --
-
 always@(posedge clk or negedge rstn)
 if(!rstn) begin
 /*AUTORESET*/
 end
 else begin
 end
-end
\ No newline at end of file
+end
diff --git a/.doom.d/snippets/verilog-mode/always (synchronous rst) b/.doom.d/snippets/verilog-mode/always(sync rst)
old mode 100644
new mode 100755
similarity index 55%
rename from .doom.d/snippets/verilog-mode/always (synchronous rst)
rename to .doom.d/snippets/verilog-mode/always(sync rst)
index a9d5a05..c213fd9
--- a/.doom.d/snippets/verilog-mode/always (synchronous rst)	
+++ b/.doom.d/snippets/verilog-mode/always(sync rst)	
@@ -1,14 +1,11 @@
 # -*- mode: snippet -*-
-# name: always (synchronous rst)
-# uuid:
-# key: trigger-key
-# condition: t
+# name: always(sync rst)
+# key:
 # --
-
 always@(posedge clk)
 if(rst) begin
 /*AUTORESET*/
 end
 else begin
 end
-end
\ No newline at end of file
+end
diff --git a/.doom.d/snippets/verilog-mode/always (synchronous rstn) b/.doom.d/snippets/verilog-mode/always(sync rstn)
old mode 100644
new mode 100755
similarity index 55%
rename from .doom.d/snippets/verilog-mode/always (synchronous rstn)
rename to .doom.d/snippets/verilog-mode/always(sync rstn)
index 1026e5a..aad0b86
--- a/.doom.d/snippets/verilog-mode/always (synchronous rstn)	
+++ b/.doom.d/snippets/verilog-mode/always(sync rstn)	
@@ -1,14 +1,11 @@
 # -*- mode: snippet -*-
-# name: always (synchronous rstn)
-# uuid:
-# key: trigger-key
-# condition: t
+# name: always(sync rstn)
+# key:
 # --
-
 always@(posedge clk)
 if(!rstn) begin
 /*AUTORESET*/
 end
 else begin
 end
-end
\ No newline at end of file
+end
diff --git a/.doom.d/snippets/verilog-mode/module(base) b/.doom.d/snippets/verilog-mode/module(base)
old mode 100644
new mode 100755
index 7dc4c54..c040a49
--- a/.doom.d/snippets/verilog-mode/module(base)
+++ b/.doom.d/snippets/verilog-mode/module(base)
@@ -1,10 +1,7 @@
 # -*- mode: snippet -*-
 # name: module(base)
-# uuid:
-# key: trigger-key
-# condition: t
+# key:
 # --
-
 module example
 #(
 parameter DIN_LEN = 8
@@ -18,4 +15,4 @@ parameter DIN_LEN = 8
 /*AUTOREG*/
 
 
-endmodule
\ No newline at end of file
+endmodule