Emacs : verilog-mode snippets fix.✡

.doom.d/snippets/verilog-mode/always(async rst)

@@ -1,14 +1,11 @@
 # -*- mode: snippet -*-
-# name: always (asynchronous rst)
-# uuid:
-# key: trigger-key
-# condition: t
+# name: always(async rst)
+# key:
 # --
-
 always@(posedge clk or posedge rst)
 if(rst) begin
 /*AUTORESET*/
 end
 else begin
 end
-end
+end

.doom.d/snippets/verilog-mode/always(async rstn)

@@ -1,14 +1,11 @@
 # -*- mode: snippet -*-
-# name: always (asynchronous rstn)
-# uuid:
-# key: trigger-key
-# condition: t
+# name: always(async rstn)
+# key:
 # --
-
 always@(posedge clk or negedge rstn)
 if(!rstn) begin
 /*AUTORESET*/
 end
 else begin
 end
-end
+end

.doom.d/snippets/verilog-mode/always(sync rst)

@@ -1,14 +1,11 @@
 # -*- mode: snippet -*-
-# name: always (synchronous rst)
-# uuid:
-# key: trigger-key
-# condition: t
+# name: always(sync rst)
+# key:
 # --
-
 always@(posedge clk)
 if(rst) begin
 /*AUTORESET*/
 end
 else begin
 end
-end
+end

.doom.d/snippets/verilog-mode/always(sync rstn)

@@ -1,14 +1,11 @@
 # -*- mode: snippet -*-
-# name: always (synchronous rstn)
-# uuid:
-# key: trigger-key
-# condition: t
+# name: always(sync rstn)
+# key:
 # --
-
 always@(posedge clk)
 if(!rstn) begin
 /*AUTORESET*/
 end
 else begin
 end
-end
+end

.doom.d/snippets/verilog-mode/module(base)

@@ -1,10 +1,7 @@
 # -*- mode: snippet -*-
 # name: module(base)
-# uuid:
-# key: trigger-key
-# condition: t
+# key:
 # --
-
 module example
 #(
 parameter DIN_LEN = 8
@@ -18,4 +15,4 @@ parameter DIN_LEN = 8
 /*AUTOREG*/
 
 
-endmodule
+endmodule