Emacs : verilog-mode snippets fix.👻

.doom.d/snippets/verilog-mode/always (asynchronous rst)

@@ -1,14 +0,0 @@
-# -*- mode: snippet -*-
-# name: always (asynchronous rst)
-# uuid:
-# key: trigger-key
-# condition: t
-# --
-
-always@(posedge clk or posedge rst)
-if(rst) begin
-/*AUTORESET*/
-end
-else begin
-end
-end

.doom.d/snippets/verilog-mode/always (asynchronous rstn)

@@ -1,14 +0,0 @@
-# -*- mode: snippet -*-
-# name: always (asynchronous rstn)
-# uuid:
-# key: trigger-key
-# condition: t
-# --
-
-always@(posedge clk or negedge rstn)
-if(!rstn) begin
-/*AUTORESET*/
-end
-else begin
-end
-end

.doom.d/snippets/verilog-mode/always (synchronous rst)

@@ -1,14 +0,0 @@
-# -*- mode: snippet -*-
-# name: always (synchronous rst)
-# uuid:
-# key: trigger-key
-# condition: t
-# --
-
-always@(posedge clk)
-if(rst) begin
-/*AUTORESET*/
-end
-else begin
-end
-end

.doom.d/snippets/verilog-mode/always (synchronous rstn)

@@ -1,14 +0,0 @@
-# -*- mode: snippet -*-
-# name: always (synchronous rstn)
-# uuid:
-# key: trigger-key
-# condition: t
-# --
-
-always@(posedge clk)
-if(!rstn) begin
-/*AUTORESET*/
-end
-else begin
-end
-end

.doom.d/snippets/verilog-mode/always(async rst)

@@ -0,0 +1,10 @@
+# -*- mode: snippet -*-
+# name: always(async rst)
+# key:
+# --
+always@(posedge clk or posedge rst) begin
+if(rst) begin
+/*AUTORESET*/
+end
+else begin
+end

.doom.d/snippets/verilog-mode/always(async rstn)

@@ -0,0 +1,10 @@
+# -*- mode: snippet -*-
+# name: always(async rstn)
+# key:
+# --
+always@(posedge clk or negedge rstn) begin
+if(!rstn) begin
+/*AUTORESET*/
+end
+else begin
+end

.doom.d/snippets/verilog-mode/always(sync rst)

@@ -0,0 +1,10 @@
+# -*- mode: snippet -*-
+# name: always(async rst)
+# key:
+# --
+always@(posedge clk) begin
+if(rst) begin
+/*AUTORESET*/
+end
+else begin
+end

.doom.d/snippets/verilog-mode/always(sync rstn)

@@ -0,0 +1,10 @@
+# -*- mode: snippet -*-
+# name: always(async rstn)
+# key:
+# --
+always@(posedge clk) begin
+if(!rstn) begin
+/*AUTORESET*/
+end
+else begin
+end

.doom.d/snippets/verilog-mode/module(base)

@@ -1,21 +1,18 @@
 # -*- mode: snippet -*-
 # name: module(base)
-# uuid:
-# key: trigger-key
-# condition: t
+# key:
 # --
-
 module example
 #(
-parameter DIN_LEN = 8
+parameter DIN_LEN=8
 )
-(/*AUTOARG*/);
+(/*AUTOARG*/)
+
+input clk, rstn;
 
 /*AUTOINPUT*/
 /*AUTOOUTPUT*/
-
 /*AUTOWIRE*/
 /*AUTOREG*/
 
-
 endmodule