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Emacs : some verilog snippets

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JaeYoo-Im
2022-06-13 11:00:23 +09:00
parent c7bbf1ff7b
commit 56c3c61e30
5 changed files with 77 additions and 0 deletions
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14
.doom.d/snippets/verilog-mode/always (asynchronous rst) Normal file
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# -*- mode: snippet -*-
# name: always (asynchronous rst)
# uuid:
# key: trigger-key
# condition: t
# --
always@(posedge clk or posedge rst)
if(rst) begin
/*AUTORESET*/
end
else begin
end
end

14
.doom.d/snippets/verilog-mode/always (asynchronous rstn) Normal file
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# -*- mode: snippet -*-
# name: always (asynchronous rstn)
# uuid:
# key: trigger-key
# condition: t
# --
always@(posedge clk or negedge rstn)
if(!rstn) begin
/*AUTORESET*/
end
else begin
end
end

14
.doom.d/snippets/verilog-mode/always (synchronous rst) Normal file
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# -*- mode: snippet -*-
# name: always (synchronous rst)
# uuid:
# key: trigger-key
# condition: t
# --
always@(posedge clk)
if(rst) begin
/*AUTORESET*/
end
else begin
end
end

14
.doom.d/snippets/verilog-mode/always (synchronous rstn) Normal file
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@ -0,0 +1,14 @@
# -*- mode: snippet -*-
# name: always (synchronous rstn)
# uuid:
# key: trigger-key
# condition: t
# --
always@(posedge clk)
if(!rstn) begin
/*AUTORESET*/
end
else begin
end
end

21
.doom.d/snippets/verilog-mode/module(base) Normal file
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# -*- mode: snippet -*-
# name: module(base)
# uuid:
# key: trigger-key
# condition: t
# --
module example
#(
parameter DIN_LEN = 8
)
(/*AUTOARG*/);
/*AUTOINPUT*/
/*AUTOOUTPUT*/
/*AUTOWIRE*/
/*AUTOREG*/
endmodule